IR2110

high and low side driver, DIP-14, 3.3V logic compatible, Floating channel, Undervoltage lockout IR2110

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Price:: US $0.10~0.60 / piece [Get Latest Price]

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PartNumber:: IR2110

Brand:: International Rectifier - IR | Pack: DIP | D/C: 08+

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Products Upload time: 2011-11-18

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Part Number:IR2110
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Product Summary

The IR2110 is a high voltage, high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.3V logic. The IR2110 features a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications.

Parametrics

IR2110 absolute maximum ratings: (1)High side floating supply voltage:-0.3V to 525V; (2)High side floating supply offset voltage:VB - 25V to VB + 0.3V; (3)High side floating output voltage:VS - 0.3V to VB + 0.3V; (4)Low side fixed supply voltage:-0.3V to 25V; (5)Low side output voltage:-0.3V to VCC + 0.3V; (6)Logic supply voltage:-0.3V to VSS + 25V; (7)Logic supply offset voltage:VCC - 25V to VCC + 0.3V; (8)Logic input voltage (HIN, LIN & SD):VSS - 0.3V to VDD + 0.3V; (9)Allowable offset supply voltage transient:50V/ns; (10)Package power dissipation @ TA ≤ +25℃:1.6W; (11)Thermal resistance, junction to ambient:75℃/W; (12)Junction temperature:150℃; (13)Storage temperature:-55℃ to 150℃; (14)Lead temperature (soldering, 10 seconds):300℃.

Features

IR2110 features: (1)Floating channel designed for bootstrap operation, Fully operational to +500V or +600V, Tolerant to negative transient voltage, dV/dt immune; (2)Gate drive supply range from 10 to 20V; (3)Undervoltage lockout for both channels; (4)3.3V logic compatible, Separate logic supply range from 3.3V to 20V, Logic and power ground ±5V offset; (5)CMOS Schmitt-triggered inputs with pull-down; (6)Cycle by cycle edge-triggered shutdown logic; (7)Matched propagation delay for both channels; (8)Outputs in phase with inputs.