S21152BB

PCI-to-PCI bridge, QFP, 3.9 V, Implements delayed transactions, memory read, S21152BB

Rated 5 Rating 5 | reviews | Write a review

Price:: US $1.00~50.00 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $1.00~50.00

PartNumber:: S21152BB

Brand:: Intel Corporation - Intel | Pack: QFP | D/C: 08+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Ms. Sally's store

(China (Mainland))

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2011-11-14

From Other Seller

Part Number:S21152BB
US $1.00 - 50.00
ECA1HHG4R7

US $10.00 - 10.00 / Piece
(0) Remove
HCPL-7800A

US $2.50 - 4.10 / Piece
(0) Remove
Quantity:

piece

Product Summary

The S21152BB is a PCI-to-PCI bridge and is fully compliant with PCI Local Bus Specification, Revision 2.1. The S21152BB is pin-to-pin compatible with the 21052, which is fully compliant with PCI Local Bus Specification, Revision 2.0.The S21152BB provides full support for delayed transactions, enabling buffering of memory read, I/O, and configuration transactions. The S21152BB has separate posted write, read data, and delayed transaction queues with significantly more buffering capability than first-generation bridges. In addition, the S21152BB supports bi-directional buffering of simultaneous multiple posted write and delayed transactions.

Parametrics

S21152BB absolute maximumratings: (1)Tj: 125℃; (2)Supply voltage, Vcc: 3.9 V; (3)Maximum voltage applied to signal pins: 5.5 V; (4)Maximum power, PWC: 1.2 W @ 33 MHz; (5)Storage temperature range, Tstg: –55 to 125℃.

Features

S21152BB features: (1)Complies fully with Revision 2.1 of the PCI Local Bus Specification; (2)Complies fully with Revision 1.1 of the PCI-to-PCI Bridge Architecture Specification; (3)Complies fully with the Advanced Configuration Power Interface (ACPI) Specification; (4)Complies fully with the PCI Power Management Specification, Revision 1.01; (5)Implements delayed transactions for all PCI configuration, I/O, and memory read commands—up to three transactions simultaneously in each direction; (6)Allows 88 bytes of buffering (data and address) for posted memory write commands in each direction—up to three transactions simultaneously in each direction.